Researchers at TU Darmstadt have introduced a fundamental shift in how embedded processors defend against side-channel attacks, proposing a hardware-level paradigm that eliminates micro-architectural leakage at its source rather than managing it through complex software countermeasures. In a newly released research paper, computer scientists Niels Wieser, Nicolai Müller, and Amir Moradi detail architectural modifications at the Register-Transfer Level (RTL) designed to allow the secure execution of cryptographic software without the performance penalties traditionally required by secure compilers and hardware-specific workarounds.
Cryptographic software has become a cornerstone of modern digital security, prized for its flexibility and adaptability in meeting rapidly evolving threat landscapes. Unlike dedicated hardware accelerators, which are often rigid and expensive to update, software-based cryptography can be patched, modified, and scaled to address new protocols and requirements. However, deploying cryptographic software on physical hardware introduces a major vulnerability: Side-Channel Analysis (SCA).
Side-channel attacks exploit physical information leaked during the execution of a cryptographic algorithm on a device. Instead of breaking the mathematical foundations of an encryption scheme, an attacker observes physical characteristics such as power consumption, electromagnetic emissions, or execution timing. By analyzing these signals, adversaries can often reconstruct secret keys and bypass security mechanisms entirely. Making cryptographic software robust against these attacks remains one of the central challenges in modern computer engineering.
To protect software implementations, cryptographers rely on a countermeasure known as masking. Masking offers provable security guarantees in theory by splitting sensitive data into multiple random shares, ensuring that no single intermediate value processed by the hardware reveals information about the secret key. Unfortunately, the theoretical perfection of masking is frequently undermined by the realities of processor micro-architectures. Modern embedded processors feature complex pipelines, caches, data forwarding paths, and internal storage structures that inadvertently combine or retain masked shares, creating unintended micro-architectural leakages.
In response to these hardware-induced vulnerabilities, the cryptographic community has adapted formal adversary models to account for micro-architectural leakage. These models typically rely on generic, yet over-conservative, assumptions about the underlying hardware. To achieve security under such broad models, software developers and compilers must generate heavily restricted code. This often involves introducing redundant operations, shuffling instructions, or inserting dummy cycles to obscure potential leakage points. While these software-level mitigations can achieve their security goals, they exact a heavy toll on performance and energy efficiency, both of which are critical constraints in resource-limited embedded systems.
To alleviate this burden, previous research focused on secure hardware-software co-design. This methodology assumes a precisely specified hardware leakage behavior, which allows compilers to apply targeted constraints rather than broad, pessimistic workarounds. While co-design successfully reduces the overhead required to counteract micro-architectural effects, it does not completely eliminate it. The software must still be engineered with a deep awareness of the hardware’s specific quirks and leakage profiles, leaving room for human error and increasing development complexity.
The new work by Wieser, Müller, and Moradi departs from this incremental approach by advocating for a fundamental change in philosophy. Rather than attempting to manage or mask leakage within the software layer, the researchers aim to eradicate it at its source. Conceptually, the team proposes specific architectural modifications to general-purpose processors at the Register-Transfer Level. By redesigning the internal logic of the processor itself, they remove the root causes of micro-architectural leakages entirely.
Implementing these structural changes enables the secure execution of standard masked software without introducing micro-architectural leakages under the Robust but Relaxed (RR) d-probing model. By shifting the burden of security from the software stack down to the silicon, the approach frees compilers from having to generate complex, security-aware instructions and eliminates the need for hardware-specific workarounds in the application code. Developers can write cleaner, more efficient software without sacrificing physical security.
Although the proposed countermeasures are designed to be broadly applicable to many different processor micro-architectures, the research team went beyond theoretical design. They formally proved the security of each individual countermeasure and integrated the modified logic into the Ibex processor, an open-source 32-bit RISC-V RV32IMC CPU core widely used in embedded systems research and commercial applications.
To validate their theoretical models and architectural designs, the researchers conducted a comprehensive evaluation of the modified Ibex processor as a complete system. This evaluation involved tool-assisted leakage assessments of the full netlist to identify any potential oversight in the logic design. Furthermore, the team performed physical experiments using Field Programmable Gate Arrays (FPGAs), measuring real-world emissions and power consumption traces to confirm that the hardware-level modifications successfully prevent side-channel leakage during the execution of masked cryptographic algorithms.
The findings are detailed in paper 2026/2478, titled "Hardware-Level Mitigation of Micro-Architectural Leakages in Embedded Processors," published on the Cryptology ePrint Archive.
